IIT Video Lectures on High Performance Computer Architecture by Dr. Rajib Mall

Video Lecture Series from IIT Professors :

High Performance Computer Architecture 

 by   Dr. Rajib Mall sir

Dr. RAJIB MALL obtained all his professional degrees: Bachelor's, Master's, and the doctoral degrees from the Indian Institute of Science, Bangalore. He worked for Motorola(India) for about three years before joining the faculty of Computer Science and Engineering at IIT, Kharagpur, where he is at present working as a professor.He has guided more than a dozen Ph.D. theses and has published more than 150 refereed international journal and conference papers. He has done consultancy projects for organizations such as General Motors, Infosys, Honeywell, and Usha Telecom. He works mostly in the areas of program analysis and testing for traditional as well as emerging software systems.

1.    Introduction

2.    A Few Basic Concepts

3.    Some More Basic Concepts

4.    Exploiting Instruction Level Parallelism

5.    Pipeline Hazards

6.    Pipeline Hazards and Their Resolution

7.    A Few Pipeline Hazard Resolution Techniques

8.    Branch Prediction Schemes

9.    Advanced Branch Prediction Techniques

10.    Software Pipelining and Predicated Instructions

11.    Software Pipelining and Predicated Instructions (Contd.)

12.    Dynamic Instructor Scheduling

13.    Tomasulo's Algorithm

14.    Speculative Execution

15.    Speculative  Execution (Contd.)

16.    Superscalar and VLIW Processors

17.    Superscalar and Vector Processors

18.    A Survey of Commercial Processors

19.    A Survey of Commercial Processors (Contd.)

20.    Basic of Memory Hierarchy

21.    Memory Hierarchy Optimization - I

22.    Memory Hierarchy Optimization - II

23.    Cache Optimizations

24.    More Cache Optimizations

25.    Some More Cache Optimizations

26.    Memory Technologies

27.    Introduction to Multiprocessors

28.    Thread and Process Level Parallelism

29.    Symmetric Multiprocessors

30.    Cache Coherency Protocols

31.    Cache Coherency Protocols (Contd.)

32.    Multiprocessor Programming Support

33.    Multithreading in Uniprocessors

34.    Computer Buses

35.    Computer Buses (Contd.)