Digital System Design
by Prof. Peter Y. K. Cheung sir
Professor of Digital Systems
Head, Department of Electrical & Electronic Engineering
Imperial College
OF SCIENCE, TECHNOLOGY
AND MEDICINE
Room 912, Electrical & Electronic Engineering
Exhibition Road
London SW7 2BT, England
Exhibition Road
London SW7 2BT, England
Phone: +44 207
594 6263
Fax: +44 207 581 4419
Email: p.cheung@imperial.ac.uk
Objectives
1. "Digital Design, Principles & Practices", J.F. Wakerly, 4th Edition (Sept 05) Prentice Hall
2. "High-Speed Digital Design - A handbook of black magic", Johnson, Graham.
3. "Contemporary Logic Design" Gaetano Boriello, Randy H. Katz, Prentice Hall, 2004
4. "FPGA-based System Design " Wayne Wolf, Prentice Hall, 2004,
- How to go about designing complex, high speed digital systems (not just circuits)?
- How to use some of the modern CAD tools to help with the design?
- How to implement such designs using programmable logic (e.g. FPGAs)?
- How to read data sheets and make sense of them?
- How do digital building blocks (such as memory chips, microprocessors, arithmetic circuits etc.) work?
- How to interface to microprocessors and computers (from hardware point of view)?
- How to deal with testing of complex systems?
1. "Digital Design, Principles & Practices", J.F. Wakerly, 4th Edition (Sept 05) Prentice Hall
2. "High-Speed Digital Design - A handbook of black magic", Johnson, Graham.
3. "Contemporary Logic Design" Gaetano Boriello, Randy H. Katz, Prentice Hall, 2004
4. "FPGA-based System Design " Wayne Wolf, Prentice Hall, 2004,
Week
|
Lectures
|
1
|
Topic 1 - Introduction & Design Methodologies
|
2
|
Topic 2 - Programmable Logic Devices
|
3
|
Topic 3 - Modern FPGA architectures
|
4
|
Topic 4 - Arithmetic Circuits
|
5
|
Topic 5 - Function Evaluation
|
6
|
Tutorial about the coursework by
Ed Stott
Framework Design Files (zipped file)
Framework Functional Description PIXEL_MAP.vhd |
7
|
Topic 6 - Clocking & Metastability
|
8
|
Topic 7 - Practical Design & I/O
Topic 8 - Memory & Memory Interfacing |
9
|
Topic 9 - JTAG Boundary Scan
|
10
|
Topic 10 - Bus Architecture
|
Supporting
materials
|
Clown
image file (zipped)
Matlab functions (rotate.m, Show.m) Ripple effect (ripple.avi) |
Cyclone
II Device Handbook, Vol. 1, p. 2-37 to 2-61
|
TI
App Notes "Designing with Logic"
XAPP133, “Using the Virtex Select I/O Resource” |
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